The invention relates to an arrangement and a method of testing an integrated circuit comprising at least two circuit sections which in normal operation operate with at least two different clock signals.
In such integrated circuits, there is the fundamental problem that temporal fluctuations affecting the mode of operation of the circuit may occur between the different clock signals. Such phase fluctuations or phase shifts may have the result, for example, that a given flip-flop in the circuit, which is clocked with a first clock, just takes over or does not take over a signal coming from a second flip-flop clocked with a second clock. These phase fluctuations or shifts which may cause such problems are known as skew in literature. To recognize such an erroneous behavior, each integrated circuit is tested after its manufacture, particularly taking the problem of skew into account. Since individual elements of the sometimes very complex integrated circuit cannot be accessed during testing, the skew problem may lead to false test results or results that cannot be evaluated. In particular, it is impossible to determine whether individual components which are critical as regards skew behavior operate flawlessly.
U.S. Pat. No. 5,349,587 discloses a test arrangement attempting to avoid this problem by activating each time only one clock signal during testing of integrated circuits operating with a plurality of clock signals. In this way, all test signals are activated one after the other so that all circuit components can be tested but the test effort increases enormously because a corresponding large number of test vectors is to be provided. This solution is therefore inappropriate for testing series manufactured integrated circuits due to the effort and the long time required for the tests.
It is an object of the invention to provide an arrangement and a method of testing integrated circuits of the type described in the opening paragraph, with which circuits operating with a plurality of clock signals can also be tested in a minimally short time and with a minimal number of test vectors.
According to the invention, this object is solved in that the integrated circuit to be tested is formed in such a way that each clock signal can be individually switched on and off during a test by test software provided in the arrangement, in that a software model of the circuit to be tested is provided in the arrangement, which software model comprises an X generator for those circuit components whose mode of operation is influenced by a plurality of clock signals and their skew behavior, which X generator is activated and supplies an X signal when more than one clock signal influencing the mode of operation of the circuit components during testing is activated, in that, during testing, the test software initially activates all clock signals and evaluates test results for those circuit components for which no X signal appears in the software model, and in that for those circuit components for which an X signal appeared in the software model during testing with all clock signals, the test software performs a plurality of test runs in which each time only one or more of the clock signals influencing the mode of operation of the circuit component is/are activated and evaluates only those tests of the circuit components of the circuit for which no X signal appears in the software model.
For the test arrangement according to the invention, the following fundamental mode of operation is used. On the one hand, there is a real integrated circuit which can be tested by means of hardware provided for this purpose in the arrangement, in which exterior signals are derived from the circuit and checked on whether they correspond to the nominal behavior of the circuit. In parallel, there is a software model for the circuit to be tested, from which the nominal behavior is known, on the one hand, and is used, on the other hand, to determine in a way to be described below which circuit components of the circuit, possibly with a plurality of simultaneously activated clock signals, can be tested.
It is assumed that the arrangement according to the invention for testing an integrated circuit is formed in such a way that each clock signal used or appearing in the integrated circuit can be individually switched on and off during testing by means of external test software in the arrangement. It should thus be possible to switch the individual clock signals on or off, as required, by means of the test software, while it should also be possible to activate possibly more clock signals simultaneously.
In known manner, the arrangement according to the invention for testing integrated circuits comprises a software model of the circuit which is provided in the integrated circuit and is to be tested. In the arrangement according to the invention, the software model is, however, formed in such a way that an X generator is provided for those circuit components whose mode of operation is influenced by a plurality of clock signals and their skew behavior. Thus, those circuit components are concerned that qualify for the above-described skew problem. This X generator is formed in the software model in such a way that it always supplies a so-called X signal when, during testing, more than one clock signal influencing the mode of operation of the relevant circuit component is activated. In other words, the X generator always supplies the X signal when the above-described skew problem might be relevant for the circuit components concerned. This is always the case when the behavior of the circuit components is dependent on the exact phase relations of the clock signals involved.
Fundamentally, an X signal appearing in the software model always signalizes a skew problem in the circuit components located in those areas where the signal appears.
During testing, the test software will initially activate all clock signals, because all components of the integrated circuit can be tested most rapidly in this way. For those circuit components for which the skew problem is to be feared, however, the assigned X generator is activated in the software model. Consequently, an X signal appears in the software model during the first test run with all activated clock signals for some circuit components. This signalizes to the test software that the test run with all activated clock signals for these circuit components does not yield any valid results. In the first test run, in which all clock signals are activated, the test results of the real integrated circuit are thus only evaluated for those circuit components for which no X signal is obtained in the software model.
For those circuit components for which an X signal is obtained in the software model, further test runs are subsequently performed, in which test runs the test software attempts, by deactivating further clock signals, to obtain effective test results for all circuit components, which results, as stated, are only present when no X signal appears for the relevant circuit components. The operation may be performed, for example, in such a way that, starting from the activation of all clock signals, clock signals are switched off one after the other in the first test run until no X signal appears any longer for the relevant circuit component. In an extreme case, this may lead to only one clock signal that may be activated until no X signal appears any longer.
It is achieved by means of the method according to the invention that valid test results are obtained for a relatively high number of circuit components in an integrated circuit already in the first test run in which all clock signals are activated. Only a relatively small number of circuits, in which invalid results are obtained in this test run, requires further test runs with clock signals deactivated one after the other. As compared with the prior art, the number of test runs is thereby considerably reduced.
An embodiment of the test arrangement according to the invention is characterized by the characterizing features as defined in claim 2. This hardware arrangement requires a relatively small number of additional circuit components to be used for testing in the integrated circuit. The circuit components provided can be realized at low cost in integrated circuits.
The above-described mode of operating the test runs can be advantageously performed for achieving a minimal number of test runs as defined in claim 3.
The object is further solved by the characteristic features as defined in claim 4 for a testing method.